1. Field of the Invention
This invention relates to SET-RESET latch circuits which produce logic latched outputs determined by SET and RESET inputs.
2. Description of the Related Art
Various types of circuits have been developed that produce and hold output states in response to input pulses. These include standard cell D-type flip-flop circuits with a clear (an example is the Motorola, Inc. MECL 10K circuit, described in MECL DATA by Motorola, Inc., 1996, page 1-5), the standard cell S-R (SET-RESET) latch (an example is described in Analog Devices, xe2x80x9cADRF ECL Cell Library Datasheetxe2x80x9d, 1996, and the solid state integrated logic flipflop or S-R latch in Taub and Schilling, xe2x80x9cDigital Integrated Electronicsxe2x80x9d, McGraw-Hill, Inc., 1977, pages 278-283.
Each of these circuits exhibits a degree of undesirable jitter and settling time in responding to control inputs. This lowers their bandwidth and makes the logic output lag undesirably behind the application of the control input.
This invention seeks to provide a precision SET-RESET logic circuit that produces a logic output whose rising and falling edges are defined precisely by the rising edges of its SET and RESET inputs, with a significant reduction in jitter and settling problems and an accompanying increase in bandwidth.
These goals are achieved by recognizing that the primary source of jitter and settling problems is in the storage element which provides a latch to maintain the output state of the S-R circuit after an input pulse has terminated. The invention removes the latch circuit from the critical signal path between the S-R inputs and the logic outputs, thus allowing for a very rapid logic response to a change in input, with the response sustained by the latch circuit once it has had an opportunity to reach a settled state. The latch circuit""s signal path is longer than the input signal paths of the SET-RESET circuit.
In a preferred implementation, the SET-RESET circuit includes two pairs of primary differential switches and a secondary differential switch. The branches of the first primary switch are respectively controlled by SET and negated SET (SETxe2x80x2) inputs, while the branches of the second primary switch are respectively controlled by RESET and negated RESET (RESETxe2x80x2) inputs. The branches of the secondary differential switch provide current paths to control conduction through the first and second primary switches, respectively. SET and RESET outputs are produced in response to the application of SET and RESET inputs to the first and second primary differential switches, respectively.
The branches of the secondary differential switch respond respectively to LATCH and LATCHxe2x80x2 inputs from the separate latch circuit. Initial current paths are established through the primary and secondary switches that control the SET and RESET outputs before the latch circuit has time to respond. The latch circuit then holds these outputs by establishing a different current path through the primary and secondary differential switches. The latch circuit itself can be designed as a cross-coupled NOR circuit, preferably with single-ended ECL (emitter coupled logic) elements.
These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.